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2m (128k x 16) static ram cy62137cv25/30/33 mobl ? cy62137cv mobl ? cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05201 rev. *c revised august 23, 2002 137cv25/3 features very high speed: 55 ns and 70 ns voltage range: ? cy62137cv25: 2.2v ? 2.7v ? cy62137cv30: 2.7v ? 3.3v ? cy62137cv33: 3.0v ? 3.6v ? cy62137cv: 2.7v ? 3.6v pin compatible with the cy62137v ultra-low active power ? typical active current: 1.5 ma @ f = 1 mhz ? typical active current: 7 ma @ f = f max (70 ns speed) low and ultra low standby power easy memory expansion with ce and oe features automatic power-down when deselected cmos for optimum speed/power packages offered in a 48-ball fbga functional description [1] the cy62137cv25/30/33 and cy62137cv are high-perfor- mance cmos static rams organized as 128k words by 16 bits. these devices feature advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular tele- phones. the devices also has an automatic power-down fea- ture that significantly reduces power consumption by 80% when addresses are not toggling. the device can also be put into standby mode reducing power consumption by more than 99% when deselected (ce high or both ble and bhe are high). the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when: deselected (ce high), out- puts are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high), or during a write operation (ce low, and we low). writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 16 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 16 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the back of this data sheet for a complete description of read and write modes. note: 1. for best practice recommendations, please refer to the cypress application note ? system design guidelines ? on http://www.cypress.com. logic block diagram 128k x 16 ram array i/o 0 ? i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 2048 x 1024 sense amps data in drivers oe a 4 a 3 i/o 8 ? i/o 15 ce we ble bhe a 16 a 0 a 1 a 9 power -down circuit bhe ble ce a 10 10
cy62137cv25/30/33 mobl ? cy62137cv mobl ? document #: 38-05201 rev. *c page 2 of 14 pin configuration [2, 3 ] maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied............................................. ? 55 c to +125 c supply voltage to ground potential ... ? 0.5v to v ccmax + 0.5v dc voltage applied to outputs in high z state [4] .................................... ? 0.5v to v cc + 0.5v dc input voltage [4] .................................... ? 0.5v to v cc + 0.5v output current into outputs (low) .............................20 ma static discharge voltage........................................... >2001v (per mil-std-883, method 3015) latch-up current.................................................... >200 ma notes: 2. nc pins are not connected to the die. 3. e3 (dnu) can be left as nc or v ss to ensure proper application. 4. v il(min.) = ? 2.0v for pulse durations less than 20 ns. 5. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25 c. we a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe v ss a 7 i/o 0 bhe nc a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 3 2 6 5 4 1 d e b a c f g h fbga (top view) a 16 dnu v cc nc operating range device range ambient temperature t a v cc cy62137cv25 industrial ? 40 c to +85 c 2.2v to 2.7v cy62137cv30 2.7v to 3.3v cy62137cv33 3.0v to 3.6v cy62137cv 2.7v to 3.6v product portfolio product v cc range (v) speed (ns) power dissipation operating, i cc (ma) standby, i sb2 ( a) f = 1 mhz f = f max v cc(min.) v cc(typ.) [5] v cc(max.) typ. [5] max. typ. [5] max. typ. [5] max. cy62137cv25ll 2.2 2.5 2.7 55 1.5 3 12 25 2 10 70 1.5 3 7 15 cy62137cv30ll 2.7 3.0 3.3 55 1.5 3 12 25 2 10 70 1.5 3 7 15 cy62137cv33ll 3.0 3.3 3.6 55 1.5 3 12 25 5 15 70 1.5 3 7 15 cy62137cvll 2.7v 3.3 3.6 70 1.5 3 7 15 5 15 cy62137cvsl 2.7v 3.3 3.6 70 1.5 3 7 15 1 5
cy62137cv25/30/33 mobl ? cy62137cv mobl ? document #: 38-05201 rev. *c page 3 of 14 electrical characteristics over the operating range parameter description test conditions cy62137cv25-55 cy62137cv25-70 min. typ. [5] max. min. typ. [5] max. unit v oh output high voltage i oh = ? 0.1 ma v cc = 2.2v 2.0 2.0 v v ol output low voltage i ol = 0.1 ma v cc = 2.2v 0.4 0.4 v v ih input high voltage 1.8 v cc + 0.3v 1.8 v cc + 0.3v v v il input low voltage ? 0.3 0.6 ? 0.3 0.6 v i ix input leakage current gnd < v i < v cc ? 1 +1 ? 1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ? 1 +1 ? 1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = 2.7v i out = 0 ma cmos levels 12 25 7 15 ma f = 1 mhz 1.5 3 1.5 3 i sb1 automatic ce power-down cur- rent ? cmos inputs ce > v cc ? 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = f max (address and data only), f=0 (oe , we , bhe , and ble ) 2 10 2 10 a i sb2 automatic ce power-down cur- rent ? cmos inputs ce > v cc ? 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 2.7v parameter description test conditions cy62137cv30-55 cy62137cv30-70 unit min. typ. [5] max. min. typ. [5] max. v oh output high voltage i oh = ? 1.0 ma v cc = 2.7v 2.4 2.4 v v ol output low voltage i ol = 2.1 ma v cc = 2.7v 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3v 2.2 v cc + 0.3v v v il input low voltage ? 0.3 0.8 ? 0.3 0.8 v i ix input leakage current gnd < v i < v cc ? 1 +1 ? 1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ? 1 +1 ? 1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = 3.3v i out = 0 ma cmos levels 12 25 7 15 ma f = 1 mhz 1.5 3 1.5 3 i sb1 automatic ce power-down cur- rent ? cmos inputs ce > v cc ? 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = f max (address and data only), f=0 (oe , we , bhe , and ble ) 2 10 2 10 a i sb2 automatic ce power-down cur- rent ? cmos inputs ce > v cc ? 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.3v
cy62137cv25/30/33 mobl ? cy62137cv mobl ? document #: 38-05201 rev. *c page 4 of 14 . electrical characteristics over the operating range (continued) parameter description test conditions cy62137cv33-55 cy62137cv33-70 cy62137cv-70 unit min. typ. [5] max. min. typ. [5] max. v oh output high voltage i oh = ? 1.0 ma v cc = 3.0v 2.4 2.4 v v cc = 2.7v 2.4 v v ol output low voltage i ol = 2.1 ma v cc = 3.0v 0.4 0.4 v v cc = 2.7v 0.4 v v ih input high voltage 2.2 v cc + 0.3v 2.2 v cc + 0.3v v v il input low voltage ? 0.3 0.8 ? 0.3 0.8 v i ix input leakage current gnd < v i < v cc ? 1 +1 ? 1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ? 1 +1 ? 1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = 3.6v i out = 0 ma cmos lev- els 12 25 7 15 ma f = 1 mhz 1.5 3 1.5 3 i sb1 automatic ce power-down current ? cmos inputs ce > v cc ? 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = f max (address and data only), f=0 (oe , we , bhe , and ble ) 5 15 5 15 a i sb2 automatic ce power-down current ? cmos inputs ce > v cc ? 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.6v ll 5 15 5 15 sl 1 5 capacitance [6] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ.) 6 pf c out output capacitance 8 pf thermal resistance description test conditions symbol bga unit thermal resistance (junction to ambient) [6] still air, soldered on a 3 x 4.5 inch, two-layer printed circuit board ja 55 c/w thermal resistance (junction to case) [6] jc 16 c/w note: 6. tested initially and after any design or process changes that may affect these parameters.
cy62137cv25/30/33 mobl ? cy62137cv mobl ? document #: 38-05201 rev. *c page 5 of 14 ac test loads and waveforms v cc typ v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% output v th equivalent to: th venin equivalent all input pulses r th r1 rise time: 1 v/ns fall time: 1 v/ns parameters 2.5v 3.0v 3.3v unit r1 16600 1105 1216 ? r2 15400 1550 1374 ? r th 8000 645 645 ? v th 1.20 1.75 1.75 v data retention characteristics (over the operating range) parameter description conditions min. typ. [5] max. unit v dr v cc for data retention 1.5 v ccmax v i ccdr data retention current v cc = 1.5v ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v 1 6 a t cdr [6] chip deselect to data retention time 0 ns t r [7] operation recovery time t rc ns data retention waveform [8] notes: 7. full device ac operation requires linear v cc ramp from v dr to v cc(min.) > 100 s or stable at v cc(min.) > 100 s. 8. bhe .ble is the and of both bhe and ble . chip can be deselected by either disabling the chip enable signals or by disabling both bhe and ble . v cc(min.) v cc(min.) t cdr v dr > 1.5 v data retention mode t r ce or v cc bhe .ble
cy62137cv25/30/33 mobl ? cy62137cv mobl ? document #: 38-05201 rev. *c page 6 of 14 switching characteristics over the operating range [9] parameter description 55 ns 70 ns unit min max min max read cycle t rc read cycle time 55 70 ns t aa address to data valid 55 70 ns t oha data hold from address change 10 10 ns t ace ce low to data valid 55 70 ns t doe oe low to data valid 25 35 ns t lzoe oe low to low z [10] 5 5 ns t hzoe oe high to high z [10, 12] 20 25 ns t lzce ce low to low z [10] 10 10 ns t hzce ce high to high z [10, 12] 20 25 ns t pu ce low to power-up 0 0 ns t pd ce high to power-down 55 70 ns t dbe bhe /ble low to data valid 55 70 ns t lzbe [11] bhe /ble low to low z [10] 5 5 ns t hzbe bhe /ble high to high z [10, 12] 20 25 ns write cycle [13] t wc write cycle time 55 70 ns t sce ce low to write end 45 60 ns t aw address set-up to write end 45 60 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 40 45 ns t bw bhe /ble pulse width 50 60 ns t sd data set-up to write end 25 30 ns t hd data hold from write end 0 0 ns t hzwe we low to high z [10, 12] 20 25 ns t lzwe we high to low z [10] 5 10 ns notes: 9. test conditions assume signal transition time of 5 ns or less, timing reference levels of v cc(typ.) /2, input pulse levels of 0 to v cc(typ.) , and output loading of the specified i ol /i oh and 30-pf load capacitance. 10. at any given temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 11. if both byte enables are toggled together this value is 10 ns. 12. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedance state. 13. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and/or ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set-up and hold timing should be referenced to the edg e of the signal that terminates the write.
cy62137cv25/30/33 mobl ? cy62137cv mobl ? document #: 38-05201 rev. *c page 7 of 14 switching waveforms notes: 14. device is continuously selected. oe , ce = v il , bhe , ble = v il . 15. we is high for read cycle. 16. address valid prior to or coincident with ce , bhe , ble transition low. address data out previous data valid data valid t rc t aa t oha read cycle no. 1 (address transition controlled) [14, 15] read cycle no. 2 (oe controlled) [15, 16] 50% 50% data valid t rc t ace t lzbe t lzce t pu data out high impedance impedance i cc i sb t hzoe t hzce t pd oe ce high v cc supply current t hzbe bhe /ble t lzoe address t doe t lzoe t dbe
cy62137cv25/30/33 mobl ? cy62137cv mobl ? document #: 38-05201 rev. *c page 8 of 14 notes: 17. data i/o is high-impedance if oe = v ih . 18. if ce goes high simultaneously with we high, the output remains in a high-impedance state. 19. during this period, the i/os are in output state and input signals should not be applied. switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 19 write cycle no. 1(we controlled) bhe /ble t bw [13, 17, 18] t hd t sd t pwe t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 19 write cycle no. 2 (ce controlled) bhe /ble t bw [13, 17, 18] t sa
cy62137cv25/30/33 mobl ? cy62137cv mobl ? document #: 38-05201 rev. *c page 9 of 14 switching waveforms (continued) data in valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 19 write cycle no. 3 (we controlled, oe low) t bw bhe /ble [18] data i/o address t hd t sd t sa t ha t aw t wc ce we data in valid write cycle no. 4 (bhe /ble controlled, oe low) [18] note 19 t bw bhe /ble t sce t pwe .
cy62137cv25/30/33 mobl ? cy62137cv mobl ? document #: 38-05201 rev. *c page 10 of 14 typical dc and ac parameters 12.0 10.0 6.0 4.0 0 8.0 i sb ( a) 12.0 10.0 6.0 4.0 2.0 2.2 0.0 8.0 i cc (ma) supply voltage (v) supply voltage (v) mobl mobl 2.2 2.0 (f = f max , (f = 1mhz) 14.0 2.5 2.7 2.5 2.7 12.0 10.0 6.0 4.0 2.0 2.7 3.3 0.0 8.0 i cc (ma) supply voltage (v) mobl (f = 1mhz) 14.0 3.0 12.0 10.0 6.0 4.0 2.0 3.0 3.6 0.0 8.0 i cc (ma) supply voltage (v) 14.0 3.3 mobl 12.0 10.0 6.0 4.0 2.7 0 8.0 supply voltage (v) 3.6 2.0 3.3 12.0 10.0 6.0 4.0 3.0 0 8.0 i sb ( a) standby current vs. supply voltage supply voltage (v) mobl 2.0 2.7 3.3 50 30 20 10 3.0 3.6 supply voltage (v) 0 40 t aa (ns) 60 3.3 50 30 20 10 2.2 0 40 t aa (ns) 60 2.5 2.7 50 30 20 10 supply voltage (v) access time vs. supply voltage 0 40 t aa (ns) 60 3.0 2.7 3.3 mobl operating current vs. supply voltage mobl mobl mobl (typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25 c) 50 30 20 10 2.7 3.6 supply voltage (v) 0 40 t aa (ns) 60 3.3 mobl supply voltage (v) (f = 1mhz) i sb ( a) 12.0 10.0 6.0 4.0 3.0 0 8.0 supply voltage (v) 3.6 2.0 3.3 mobl i sb ( a) 55 ns) (f = f max , 70 ns) (f = f max , 70 ns) (f = f max , 55 ns) (f = f max , 70 ns) (f = f max , 55 ns) 12.0 10.0 6.0 4.0 2.0 2.7 3.6 0.0 8.0 i cc (ma) supply voltage (v) 14.0 3.3 mobl (f = 1mhz) (f = f max , 70 ns) ll sl
cy62137cv25/30/33 mobl ? cy62137cv mobl ? document #: 38-05201 rev. *c page 11 of 14 truth table ce we oe bhe ble inputs/outputs mode power h x x x x high z deselect/power-down standby (i sb ) x x x h h high z deselect/power-down standby (i sb ) l h l l l data out (i/o o ? i/o 15 ) read active (i cc ) l h l h l data out (i/o o ? i/o 7 ); i/o 8 ? i/o 15 in high z read active (i cc ) l h l l h data out (i/o 8 ? i/o 15 ); i/o 0 ? i/o 7 in high z read active (i cc ) l h h l l high z output disabled active (i cc ) l h h h l high z output disabled active (i cc ) l h h l h high z output disabled active (i cc ) l l x l l data in (i/o o ? i/o 15 ) write active (i cc ) l l x h l data in (i/o o ? i/o 7 ); i/o 8 ? i/o 15 in high z write active (i cc ) l l x l h data in (i/o 8 ? i/o 15 ); i/o 0 ? i/o 7 in high z write active (i cc ) ordering information speed (ns) ordering code voltage range (v) package name package type operating range 70 cy62137cv25ll-70bai 2.2 ? 2.7 ba48a 48-ball fine pitch bga (7 mm x 7 mm x 1.2 mm) industrial cy62137cv25ll-70bvi 2.2 ? 2.7 bv48a 48-ball fine pitch bga (6 mm x 8 mm x 1 mm) CY62137CV30LL-70BAI 2.7 ? 3.3 ba48a 48-ball fine pitch bga (7 mm x 7 mm x 1.2 mm) cy62137cv30ll-70bvi 2.7 ? 3.3 bv48a 48-ball fine pitch bga (6 mm x 8 mm x 1 mm) cy62137cv33ll-70bai 3.0 ? 3.6 ba48a 48-ball fine pitch bga (7 mm x 7 mm x 1.2 mm) cy62137cv33ll-70bvi 3.0 ? 3.6 bv48a 48-ball fine pitch bga (6 mm x 8 mm x 1 mm) cy62137cvll-70bai 2.7 ? 3.6 ba48a 48-ball fine pitch bga (7 mm x 7 mm x 1.2 mm) cy62137cvll-70bvi 2.7 ? 3.6 bv48a 48-ball fine pitch bga (6 mm x 8 mm x 1 mm) cy62137cvsl-70bai 2.7 ? 3.6 ba48a 48-ball fine pitch bga (7 mm x 7 mm x 1.2 mm) cy62137cvsl-70bvi 2.7 ? 3.6 bv48a 48-ball fine pitch bga (6 mm x 8 mm x 1 mm) 55 cy62137cv25ll-55bai 2.2 ? 2.7 ba48a 48-ball fine pitch bga (7 mm x 7 mm x 1.2 mm) cy62137cv25ll-55bvi 2.2 ? 2.7 bv48a 48-ball fine pitch bga (6 mm x 8 mm x 1 mm) cy62137cv30ll-55bai 2.7 ? 3.3 ba48a 48-ball fine pitch bga (7 mm x 7 mm x 1.2 mm) cy62137cv30ll-55bvi 2.7 ? 3.3 bv48a 48-ball fine pitch bga (6 mm x 8 mm x 1 mm) cy62137cv33ll-55bai 3.0 ? 3.6 ba48a 48-ball fine pitch bga (7 mm x 7 mm x 1.2 mm) cy62137cv33ll-55bvi 3.0 ? 3.6 bv48a 48-ball fine pitch bga (6 mm x 8 mm x 1 mm)
cy62137cv25/30/33 mobl ? cy62137cv mobl ? document #: 38-05201 rev. *c page 12 of 14 package diagrams 48-ball (7.00 mm x 7.00 mm x 1.2 mm) fbga ba48a 51-85096-*e
cy62137cv25/30/33 mobl ? cy62137cv mobl ? document #: 38-05201 rev. *c page 13 of 14 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. mobl is a registered trademark and more battery life is a trademark of cypress semiconductor corporation. all product and company names mentioned in this document may be the trademarks of their respective holders. package diagrams (continued) 48-lead vfbga (6 x 8 x 1 mm) bv48a 51-85150-*a
cy62137cv25/30/33 mobl ? cy62137cv mobl ? document #: 38-05201 rev. *c page 14 of 14 document title: cy62137cv25/30/33 mobl ? and cy62137cv mobl ? 2m (128k x 16) static ram document number: 38-05201 rev. ecn no. issue date orig. of change description of change ** 112393 02/19/02 gav new data sheet-advance information *a 114015 04/25/02 jui add bv package diagram. change from advance information to preliminary *b 117064 07/12/02 mgn change from preliminary to final *c 118122 09/10/02 mgn add new part number - cy62137cv with wider voltage (2.7v - 3.6v). add new sl power bin for new part #. for t aa = 55 ns, improved t pwe min from 45 ns to 40 ns. for t aa = 70 ns, improved t pwe min from 50 ns to 45 ns. for t aa = 70 ns, improved t lzwe min from 5 ns to 10 ns.

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